Chip Design
(4.9 Reviews)
Starting On :   04th Feb, 2025 
VLSI Design Flow
Course Description
The Internship/Training Program on VLSI Design Flow (RTL to GDS-II) is an intensive, hands-on program designed to provide comprehensive knowledge of the VLSI design process. It covers every stage of the design flow, from Register Transfer Level (RTL) design to the final chip layout (GDS-II), making it an ideal program for students and professionals aiming to build a strong foundation in the semiconductor industry.
What you'll learn in this course?
- Understanding RTL Design: Learn the basics of Register Transfer Level design, the starting point of VLSI design.
- Synthesis Process: Gain expertise in converting RTL designs into gate-level netlists.
- Physical Design: Explore placement, routing, and optimization techniques for efficient chip layout.
- Timing Analysis: Master Static Timing Analysis (STA) to ensure design reliability.
- Final Chip Layout: Create GDS-II files, the industry-standard format for final chip design.
- Hands-On Tools: Get practical experience with industry-leading tools used in the VLSI design process.
Duration & Timing
Program Length: 30 working days (6 weeks)
Daily Schedule:
- 1 Hour: Theory session
- 1 Hour: Practical session
- 1 Hour: Additional lab access
Total Training Hours: Over 90 hours of comprehensive learning and hands-on experience.
Week-Wise Course Modules:
Module 1: Basic Concepts of Digital Electronics
✔ Introduction to basic logic circuits
✔ Logic gates (AND, OR, NOT, NAND, NOR, Ex-OR, Ex-NOR) and their truth tables
✔ Universal gates
✔ Combinational logic
✔ CMOS, CMOS as an inverter, NAND gate
Module 2: Sequential Circuits
✔ Flip-flops (D, T, SR)
✔ Registers
✔ Counters (Synchronous/Asynchronous)
✔ Up/down synchronous counters
✔ Applications of counters
Module 3: Overview of VLSI Design Flow
✔ Role of logic synthesis in VLSI
✔ Terminologies associated with netlists
✔ Tasks like RTL synthesis, logic optimization, and technology mapping
Module 4: Overview of Physical Design in VLSI
✔ Chip planning
✔ Placement
✔ Clock tree synthesis (CTS)
✔ Routing
Module 5: Hardware Modeling using Verilog
✔ HDL for combinational circuits
Module 6: Hardware Modeling using Verilog
✔ Distinct features of HDLs vs high-level programming languages
✔ Introduction to Verilog language
✔ Nets, variables, vectors, and arrays
Module 7: Hardware Modeling using Verilog II
✔ Verilog language constructs (modules, ports, instantiation, parameterized modules)
✔ Operators, expressions, conditional blocks, loop controls
✔ Initial and always blocks
✔ Functions and tasks
✔ Continuous, blocking, and non-blocking assignments
Module 8: RTL Synthesis I
✔ Tasks in RTL synthesis: lexical analysis, parsing, elaboration, translation, and optimization
✔ Synthesis of assign statements, conditional blocks, always blocks, flip-flops, and latches
Module 9: Logic Optimization I
✔ Two-level logic minimization for Boolean functions
✔ Heuristic two-level logic minimization
Module 10: Logic Optimization II
✔ Multi-level logic minimization
✔ Transformations (simplify, eliminate, substitute, extract)
✔ Challenges of optimizing using algebraic vs Boolean models
Module 11: Static Timing Analysis
✔ Basic concepts and motivation
✔ Arrival time and required time calculation
✔ Slack computation
Module 12: Mechanics of STA
✔ Analyzing timing reports
✔ Corrective measures
✔ Paths in circuits
Module 13: Advanced STA Concepts
✔ Slew propagation (graph-based and path-based analysis)
✔ Multi-mode multi-corner (MMMC) analysis
✔ On-chip variations (OCV) and derating factors
Module 14: Constraints in VLSI Design
✔ Synopsys Design Constraints (SDC)
✔ Clock sources, latency, uncertainty, and transition
Module 15: Technology Mapping
✔ Trade-offs, opportunities, and challenges in technology mapping
Module 16: Basic Concepts for Physical Design
✔ Antenna effect
✔ Library Exchange Format (LEF) file information
Module 17: Floorplanning, Clock Tree Synthesis, and Routing
✔ Clock tree synthesis (minimizing clock skew)
✔ Global and local clock distribution networks
Tutorial 1: Introduction to Linux
✔ Creating a Linux environment using Windows Subsystem for Linux (WSL)
✔ Basic Unix commands
Tutorial 2: Introduction to iverilog
✔ Simulation using iverilog
Tutorial 3: Synthesis using Yosys I
✔ Hands-on synthesis using Yosys (tentative)
Tutorial 4: Synthesis using Yosys II
✔ Advanced synthesis using Yosys (tentative)
Tutorial 5: STA using OpenSTA I
✔ Hands-on STA analysis using OpenSTA (tentative)
Tutorial 6: Physical Design using OpenRoad I
✔ Hands-on physical design using OpenRoad (tentative)
Eligibility Criteria
We welcome applications from a wide range of individuals with a background in relevant technical fields. To be eligible for this program, candidates must meet the following requirements:
- Educational Qualifications:
- B.Tech / M.Tech / B.Sc / M.Sc in a relevant discipline.
- Diploma in a relevant field with a minimum of two years of industry experience.
- Additional Categories:
- Research Scholars, Faculty Members, and Industry Professionals are also welcome to enroll in this program.
This program is designed to accommodate professionals and academic individuals looking to expand their knowledge and skills in the field.



- Yosys
- Magic
- iVerilog
- OpenSTA/ OpenTimer

CoE in Chip Design, NIELIT Noida
Mr. Prashant Pal is a seasoned expert in the field of chip design with extensive experience in both academia and industry. As the Deputy Director and Scientist C at NIELIT Noida’s Centre of Excellence in Chip Design, he plays a pivotal role in advancing research and development in semiconductor technologies. With a deep understanding of VLSI design, he has successfully guided numerous projects and contributed to the development of cutting-edge solutions. His expertise and passion for chip design make him a highly respected mentor and instructor.

Course Fee:
2,700
Course Includes:
- Level Intermediate
- Duration 90hr
- Sessions 60
- Mode Online
- Certification Yes
Frequently Asked Questions
Have questions? Find quick and clear answers to the most common queries in our FAQ section. Whether it’s about our programs, services, or initiatives, we’re here to provide the information you need to stay informed.”
Yes, we offer a 10% group discount for a minimum of 5 students or working professionals from the same university, institute, or company.
The Certification Programme in VLSI Design Flow incorporates industry-leading tools and resources to provide practical training in ASIC design workflows.
Genus: For logic synthesis and RTL design optimization.
Innovus: For physical design tasks like floor planning, placement, routing, and clock tree synthesis.
Tempus: For static timing analysis and timing closure.
Yes, we offer a two-part installment option for the course fees. For more details, please refer to the registration page.