Functional Verification with System Verilog and UVM
The In-Campus Certification Programme in Functional Verification with SystemVerilog and UVM offers hands-on training in VLSI verification and semiconductor technology, equipping students and professionals with the skills and knowledge needed for a career in functional verification and design validation.
COURSE OVERVIEW
The Certification Programme in Functional Verification with SystemVerilog and UVM (In-Campus Mode) is an intensive, hands-on training program designed for students and professionals aiming to build a career in VLSI verification and semiconductor technology. This program offers a deep dive into the principles and methodologies of functional verification using industry-standard tools and languages such as SystemVerilog and the Universal Verification Methodology (UVM). Participants will gain both theoretical understanding and practical expertise necessary to verify complex digital designs in today’s semiconductor industry.
Course Fees:
Smart Investment, Bright Future-
Incl.GST
FUNCTIONAL VERIFICATION WITH SYSTEM VERILOG AND UVM (In-Campus Mode):
Module 1: Introduction to Verilog
- Origins, Overview, Need and Importance
- Verilog Data
- Basic Verilog example .
Module 2: Introduction to System Verilog
- Origins, Overview, Need and Importance. Introduction System Verilog Verification environment .
- Data types In system Verilog
- Array Handling, Dynamic Array, Associative Array, Queues in System Verilog
Module 3: Task and functions in system verilog
- Void function in System
- Different type of loops in SV.
Module 4: Randomization
- Randomization in real world
- Randomization in System Verilog
- Random variables
Module 5:Coverage
- Understanding Coverage
- Methodology
- Code Coverage
- Types of code coverages
Module 6:Introduction to the AMBA APB Protocol
- Sharing of specs
- Understanding the signals .
Module 7:Introduction to Universal Verification Methodology (UVM)
- Coverage-Driven Verification (CDV)
- UVM testbenches and environments
- Verification components:
- Data Item (Transaction)
- Driver (BFM)
- Sequencer
Capstone Project:
Outcomes:
- The objective of the course is to take a lab oriented hands on practical approach for learning FUNCTIONAL VERIFICATION WITH SYSTEM VERILOG AND UVM via examples with more complete discussion. Numerous examples are provided to Learn and Re-Learn.
Eligibility Criteria
This program on Functional Verification with SystemVerilog and UVM is designed to cater to a broad and diverse audience with an interest in VLSI design and verification:
- Undergraduate and Postgraduate Students:
Students currently pursuing or who have completed B.E/B.Tech./M.Sc./M.Tech in Electronics & Communication Engineering, Electrical Engineering, Computer Science, or related domains, looking to build strong fundamentals in digital design and verification methodologies. - Recent Graduates:
Individuals aiming to launch a career in the semiconductor industry, particularly in the domain of ASIC/FPGA design and verification, and seeking industry-relevant practical training in SystemVerilog and UVM. - Research Scholars:
Researchers working in VLSI, digital design, or verification-related projects who want to enhance their understanding and hands-on skills in functional verification methodologies. - Faculty Members:
Academic professionals interested in updating their curriculum or research initiatives with advanced knowledge in SystemVerilog and UVM-based verification environments. - Industry Professionals:
Working professionals in electronics, embedded systems, or chip design sectors who seek to upskill or transition into roles focused on verification, including those using modern methodologies like UVM (Universal Verification Methodology).
- Undergraduate and Postgraduate Students:
Key Tools Covered in the Program:
Cadence Xcelium:
- Cadence Xcelium Simulator – High-performance logic simulation for SystemVerilog and UVM-based environments.
- SimVision Debugger – Waveform viewer and debugger used alongside Xcelium for analyzing simulation results.
- UVM (Universal Verification Methodology) Libraries – Framework for building reusable and scalable testbenches.
- SystemVerilog Language Support – Used for testbench development, functional coverage, assertions, and randomization.
- Automation with Makefiles/Scripts – Simplifies compilation, simulation, and regression workflows.
- Hands-on Lab Sessions – Practical implementation of verification using Xcelium tools and methodologies.
These tools collectively provide participants with hands-on experience in developing, simulating, and debugging UVM-based verification environments, in alignment with industry standards and best practices in functional verification.
Is there any discount available?
Yes, we offer a 10% group discount for students and working professionals from the same university or institute.
What Libraries and Tools are Used in the Courses?
The Certification Programme in Functional Verification leverages industry-standard tools and methodologies to provide practical training in SystemVerilog and UVM-based verification workflows.
Cadence Xcelium:These tools collectively provide participants with hands-on experience in developing, simulating, and debugging UVM-based verification environments, in alignment with industry standards and best practices in functional verification.
Do you have an EMI/Installment Option Available?
Yes, we offer a two-part installment option for the course fees. For more details, please refer to the registration page.
Will a certificate be provided for this course?
Yes, certificates will be provided after successful completion of course and it’s assessment.
Course Delivery Model
- Instructor-led live classes
- Instructor-led hands-on lab sessions
- Content Access through e-Learning portal
- Assessment and Certification .
VLSI Tools
- Cadence Xcelium
Eligibility
- Students who have completed or pursuing B.E/B.Tech./M.Sc./M.Tech in, Electronics & Communication Engineering, Electrical Engineering, Computer Science or relevant fields
- Recent graduates/Faculty members seeking to enter the semiconductor industry
- Research Scholars, Faculty members, and Industry professionals can also enroll
Payments
- Pay through Debit card/ Credit card/ Net banking/ UPI.
- Attractive Discount for Group of 5 Students or more from the same College/Institution/University
Registration Process
- Candidates have to apply in the prescribed application form through https://regn.nielitvte.edu.in/in_campus_courses.php.
- The duly filled form along with the course fees receipt has to be submitted in online mode through the above link. The Fees deposited are Non-Refundable.
Course Cordinator
- PRASHANT PAL
- Deputy Director/Scientist C
- CoE in Chip Design, NIELIT Noida
- e-mail: prashantpal@nielit.gov.in
What makes UVM the preferred choice for functional verification?
UVM offers a standardized, reusable framework that simplifies the creation of complex testbenches using SystemVerilog. Its support for constrained random testing, functional coverage, and modular components enables faster, more thorough verification—making it the go-to methodology for ASIC and FPGA projects in the semiconductor industry.
